Increased capacitance trench capacitor

ABSTRACT

Disclosed is a method of increasing the capacitance of a trench capacitor by increasing sidewall area, comprising: forming a trench in a silicon substrate, the trench having a sidewall; forming islands on the sidewall of the trench; and etching pits into the sidewall using the islands as a mask. The capacitor is completed by forming a node insulator on said on the pits and the sidewall; and filling said trench with a trench conductor.

DETAILED DESCRIPTION OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of trench capacitorsfor integrated circuits; more specifically, it relates to trenchcapacitors having an increased plate area and methods of fabricatingsaid trench capacitors.

[0003] 2. Background of the Invention

[0004] Dynamic random access memories (DRAM) are widely used in computertechnology. Typically, the DRAM cells are used to store data in the formof bits. DRAMs store bits as charge (or the absence of charge) on acapacitor. Since the charge can leak off, DRAMs must be periodicallyrefreshed. Refreshing consumes power and time. Additionally, as DRAMperformance has increased cell size, and horizontal capacitor size hasdecreased. Decreasing the size of the capacitor results in less chargebeing stored, making the cell more difficult to read as well as moresensitive to leakage.

[0005] One type of capacitor used for DRAMs is a trench capacitor. Atrench capacitor is formed by forming a trench in a silicon substrate,lining the sidewalls of the trench with a dielectric and filling thetrench with a conductive material. The substrate acts as one plate ofthe capacitor and the conductive fill as the second plate. Thecapacitance of a trench capacitor is a function of the dielectricthickness and the surface area of the trench sidewalls and bottom, whichdefine the plate area as given by C=εA/d, where C is the capacitance, εis the dielectric constant of the dielectric layer, d is the thicknessof the dielectric layer and A is the surface area of the plates.

[0006] Capacitance of a trench capacitor may be increased in severalways. First, the dielectric layer may be made thinner, but leakagebecomes a concern. Second, the dielectric may be selected to have a highdielectric constant, but such exotic materials are hard to control andincorporate into DRAM technology. Third, the area of the plates may beincreased. Since the area of the plates has been decreasing by reducinghorizontal dimension of the trench capacitor, increasing the verticaldepth of the trench capacitor has indeed been done. However, there aretechnology limits as to how deep a trench can be etched in siliconbefore vertical etch depth does not increase significantly withincreased etch time and blow out of horizontal dimensions occurs.Further very deep trenches are difficult to fill.

SUMMARY OF THE INVENTION

[0007] A first aspect of the present invention is a method of increasingthe capacitance of a trench capacitor by increasing sidewall area,comprising: forming a trench in a silicon substrate, the trench having asidewall; forming islands on the sidewall of the trench; and etchingpits into the sidewall using the islands as a mask.

[0008] A second aspect of the present invention is a method offabricating a trench capacitor, comprising: forming a trench in asilicon substrate, the trench having a sidewall; forming islands on thesidewall of the trench; etching pits into the sidewall using the islandsas a mask; forming a node insulator on the pits and the sidewall; andfilling the trench with a trench conductor.

[0009] A third aspect of the present invention is a trench capacitor,comprising: a trench in a silicon substrate, the trench having asidewall; pits etched into the sidewall; a node insulator on the pitsand the sidewall; and a trench conductor filling the trench.

[0010] A fourth aspect of the present invention is a dynamic randomaccess memory cell, comprising: a FET comprising: a first and secondsource/drain region formed in a silicon substrate; a channel regionbetween the first and second source/drain regions; a gate dielectricformed over the channel region; a wordline formed over the gatedielectric; and a bitline electrically connected to the firstsource/drain; a trench capacitor comprising: a trench in the siliconsubstrate, the trench having a sidewall; pits etched into the sidewall;a node insulator on the pits and the sidewall; and a trench conductorfilling the trench.; and the second source/drain electrically connectedto the trench conductor.

BRIEF DESCRIPTION OF DRAWINGS

[0011] The features of the invention are set forth in the appendedclaims. The invention itself, however, will be best understood byreference to the following detailed description of an illustrativeembodiment when read in conjunction with the accompanying drawings,wherein:

[0012]FIGS. 1 through 10 are cross-sectional views illustratingfabrication of a trench capacitor according to a first embodiment of thepresent invention; FIGS. 11 and 12 are cross-sectional viewsillustrating fabrication of a trench capacitor according to a secondembodiment of the present invention; and

[0013]FIG. 13 is a partial cross sectional view of a dynamic randomaccess memory (DRAM) cell utilizing the trench capacitor of the presentinvention as a charge storage device.

DETAILED DESCRIPTION OF THE INVENTION

[0014]FIGS. 1 through 10 are cross-sectional views illustratingfabrication of a trench capacitor according to a first embodiment of thepresent invention. In FIG. 1, a pad oxide layer 100 has is formed on atop surface 105 of a silicon substrate 110. A mask layer 115 is formedon a top surface 120 of pad oxide layer 100. A trench 125 is formed inpad oxide layer 100 and mask layer 115 exposing top surface 105 ofsilicon substrate 110 at the bottom of the trench. In one example, padoxide layer 100 is silicon oxide formed by a thermal oxidation processand is about 100 Å thick and mask layer 115 is a dual layer of about5,000 Å to 10,000 Å of silicon oxide formed over about 1200 Å of siliconnitride, both the silicon oxide and silicon nitride formed by chemicalvapor deposition (CVD) processes. Pad oxide layer 100 serves to protecttop surface 105 of silicon substrate 110 from contamination while masklayer 115 is a hard mask for etching silicon substrate 110.

[0015] In FIG. 2, a trench 130 is etched in silicon substrate 110. Inone example, trench 130 is about 6 to 12 microns deep and is etched by areactive ion etch (RIE) process using an HBR/O2 gas mixture.

[0016] In FIG. 3, a thin mask layer 135 is formed on sidewalls 140 andbottom 145 of trench 130. In one example, thin mask layer 135 is about10 to 100 Å of silicon oxide formed by a thermal oxidation process.

[0017]FIGS. 4 and 5 illustrate the process of forming a conglomeratelayer, having particulates embedded in a matrix, on top of thin masklayer 135. In FIG. 4, a precursor layer 150 is formed over thin mask135. In FIG. 5, precursor layer 150 is converted to a conglomerate layer150A. In one example, conglomerate layer 150A comprises Ge nanocrystalls(nc-Ge) in a SiO₂ matrix. Several methods exist for forming precursorlayer 150 and for converting the precursor layer to conglomerate layer150A.

[0018] In a first method, precursor layer 150 comprises a layer ofSi_(1−x)Ge_(x) (in one example, x=0.58 to 0.85) formed by low-pressurechemical vapor deposition (LPCVD) using SiH₄ and GeH₄ gases at about 600to 800° C. Precursor layer 150 is about 10 to 100 Å thick. TheSi_(1−x)Ge_(x) is converted to Si_(1−x)Ge_(x)O₂ (in one example, x=0.58to 0.85) by a high-pressure oxidation (about 25 MPa) using H₂0 at about475° C. Then, the Si_(1−x)Ge_(x) is converted to nc-Ge in a SiO₂ layer150A by low-pressure (about 0.1 MPa) rapid thermal anneal (RTA) in H₂ or20% H₂ in N₂ for about 1 to 120 minutes. The nanocrystalls of Ge areabout 10 to 100 Å in size.

[0019] In a second method, precursor layer 150 comprises a layer ofgermosilicate glass (GSG=GeO_(x) mixed with SiO_(x)) formed byatmospheric pressure chemical vapor deposition (APCVD) usingtetraethoxysilicate (TEOS=Si(OC₂H₅)₄), timethylgerminate (TMG=Ge(OCH₃)₃)and O₃ at about 415° C. Precursor layer 150 is about 10 to 100 Å thick.The GSG is then converted to nc-Ge in SiO₂ layer 150A by annealing inhydrogen for about 60 to 120 minutes at about 700 to 800° C. Thenanocrystalls of Ge are about 10 to 100 Å in size.

[0020] In FIG. 6, most of the SiO₂ matrix of Ge in SiO₂ layer 150A aswell as portions of thin mask layer 135 is etched away leaving nc-Gecrystals 155 over islands 160 wherever the nc-Ge crystals protect thethin mask layer from the etch process to expose silicon substrate 110 onsidewalls 140 and bottom 145 of trench 130 between the islands. Some ofthe Si0₂ matrix between nc-Ge crystals 155 and thin mask layer 135remains, being protected by the nc-Ge crystals. A 200 or more:1 diluteaqueous dilute HF may be used etching exposed portions of thin masklayer 135 to form islands 160. An RIE etch may be used, but it wouldneed to etch SiO₂ selective to Ge.

[0021] In FIG. 7, pits 165 are formed in silicon substrate 110 whereversilicon substrate 110 is exposed between islands 160. Pits 165 may beformed by one of two processes. In the first process, a Si selective toGe and SiO₂ plasma etch process is used to form pits 165. Examples of aSi selective to Ge and SiO₂ plasma etch process include a SF₆/O₂chemistry where O₂ is less than 50% of the total gas volume and a SF₆(35 sccm)/H2 (65 sccm)/CF₄ (80 sccm) chemistry at 75 watts or lower RFpower. In a second process, a Si selective to SiO₂ but not selective toGe is used to form pits 165. An example of a Si selective to SiO₂ butnot selective to Ge is a SF₆/O₂ chemistry where O₂ is greater than 50%of the total gas volume. Using the second process, nc-Ge crystals 155are partially or totally etched away as pits 165 are formed.

[0022] In FIG. 8, nc-Ge crystals 155 and islands 160 are etched away. Ifnc-Ge crystals 155 were not etched away during formation of pits 165 thenc-Ge crystals are etched away now using one of the Si/Ge etch plasmachemistries indicated above. Islands 160 are etched away by using about100:1 to 200 to 1 aqueous dilute HF.

[0023] In FIG. 9, pad oxide layer 100 and any remaining mask layer 15are removed and a conformal node insulator layer 170 is formed on allexposed silicon surfaces in trench 130. Optionally, as a surfacepreclean before node insulator formation, about 10 to 20 Å ofsacrificial oxide may be formed on on sidewalls 140 and bottom 145 oftrench 130 as well on all surfaces of pits 165 and then removed usingabout 100:1 to 200 to 1 aqueous dilute HF. Node insulator layer 170 isformed over all surfaces of pits 165, and over remaining portions ofsidewalls 140 and bottom 145 of trench 130. Node insulator layer 170 iscontinuous in trench 130. In one example, node insulator layer 170 iscomprised of a dual layer of about 50 Å or less of silicon nitride overabout 50 Å or less of silicon oxide. In a second example, node insulatorlayer 170 is comprised of about 50 Å or less of silicon oxide. In athird example, node insulator layer 170 is comprised of about 50 Å orless of silicon oxynitride.

[0024] In FIG. 10, trench 130 is filled with a trench conductor 175.Trench conductor 175 may be formed by a CVD process followed by achemical mechanical polish (CMP) step to make a top surface 180 of thetrench conductor co-planer with top surface 105 of silicon substrate110. In one example, trench conductor 175 is comprised of tungsten orpolysilicon (N or P doped or undoped), tungsten nitride, titaniumnitride or other refractory metal or metal compound. A trench capacitor185 has thereby been formed. Trench conductor 175 forms a first plate,silicon substrate 110 forms a second plate and node insulator 170 formsthe dielectric of trench capacitor 185. Since the storage capacity of acapacitor is directly related to the surface area of the plates trenchcapacitor 185 has increased capacitance over of trench capacitor havingsmooth sidewalls because of the increased surface area due to etch pits165.

[0025]FIGS. 11 and 12 are cross-sectional views illustrating fabricationof a trench capacitor according to a second embodiment of the presentinvention. FIG. 10 corresponds to FIG. 6 and FIG. 11 corresponds to FIG.7 of the first embodiment. The steps illustrated in FIGS. 1 through 5and 8 through 10 and described above apply to the second embodiment aswell.

[0026] In FIG. 11, nc-Ge crystals 155 are removed using a C12 plasmaetch process leaving pits 165A in layer 150A.

[0027] In FIG. 12, pits 165 are formed in silicon substrate 110 by firstetching through thin mask layer 135 and then etching silicon substrate110 as described above.

[0028]FIG. 13 is a partial cross sectional view of a DRAM cell utilizingthe trench capacitor of the present invention as a charge storagedevice. In FIG. 11, DRAM cell 200 comprises trench capacitor 185 formedin a P+ silicon substrate 190. Also formed in silicon substrate 190 is ashallow trench isolation (STI) 195 abutting a first side 200A of trenchcapacitor 185 and an N-well 205 abutting a second side 200B of thetrench capacitor. Formed in N-well 205 are a first P+ source/drain 210and a second P+ source/drain 215 separated by a channel region 220.Second source drain 215 abuts second side 200B of trench capacitor 185.Formed over channel region 220 is a gate dielectric 225 and formed overgate dielectric 225 is a wordline 230 (which also acts a pass-gate.)Formed over STI 195 is a passing wordline 235. A conductive strap 240electrically connects second source drain 215 to trench conductor 175.Trench capacitor 185 includes an insulating collar 242 extending fromstrap 240 past N-well 205 into substrate 190. A bitline 245 is formedover an insulating layer 250. Bitline 245 is electrically connected tofirst source/drain 210 by a bitline contact 255. The operation of DRAMcell 200 is well known to those skilled in the art.

[0029] The description of the embodiments of the present invention isgiven above for the understanding of the present invention. It will beunderstood that the invention is not limited to the particularembodiments described herein, but is capable of various modifications,rearrangements and substitutions as will now become apparent to thoseskilled in the art without departing from the scope of the invention.Therefore it is intended that the following claims cover all suchmodifications and changes as fall within the true spirit and scope ofthe invention.

What is claimed is:
 1. A method of increasing the capacitance of atrench capacitor by increasing sidewall area, comprising: forming atrench in a silicon substrate, said trench having a sidewall; formingislands on said sidewall of said trench; and etching pits into saidsidewall using said islands as a mask.
 2. The method of claim 1, whereinforming islands on said sidewalls of said trench comprises: forming amask layer on said sidewall of said trench; forming a precursor layer onsaid mask layer; converting said precursor layer to a conglomerate layercomprised of particulates in a matrix; removing said matrix from betweensaid particulates to expose portions of said mask layer; and removingportions of exposed mask layer to form said islands.
 3. The method ofclaim 2, wherein said mask layer is a thin silicon oxide.
 4. The methodof claim 2, wherein said particulates are crystalline.
 5. The method ofclaim 2, wherein said precursor layer is selected from the groupconsisting of Si_(1−x)Ge_(x) and germosilicate glass.
 6. The method ofclaim 2, wherein said conglomerate layer comprises Ge nanocrystalls in asilicon oxide matrix.
 7. The method of claim 2, wherein: said precursorlayer comprises Si_(1−x)Ge_(x) formed by low-pressure chemical vapordeposition; said conglomerate layer comprises Ge nanocrystalls in asilicon oxide matrix; and said precursor layer is converted to saidconglomerate layer by a high-pressure oxidation followed by a reductionin hydrogen.
 8. The method of claim 2, wherein: said precursor layercomprises germosilicate glass formed by atmospheric pressure chemicalvapor deposition; said conglomerate layer comprises Ge nanocrystalls ina silicon oxide matrix; and said precursor layer is converted to saidconglomerate layer by annealing in hydrogen.
 9. The method of claim 2,wherein said precursor layer is between 10 and 100 Å thick.
 10. Themethod of claim 2, wherein said particulates are removed simultaneouslywith the etching of said pits.
 11. The method of claim 2, wherein saidparticulates are between 10 and 100 Å in size.
 12. The method of claim6, wherein said Ge nanocrystalls are between 10 and 100 Å in size.
 13. Amethod of fabricating a trench capacitor, comprising: forming a trenchin a silicon substrate, said trench having a sidewall; forming islandson said sidewall of said trench; etching pits into said sidewall usingsaid islands as a mask; forming a node insulator on said pits and saidsidewall; and filling said trench with a trench conductor.
 14. Themethod of claim 13, wherein forming islands on said sidewalls of saidtrench comprises: forming a mask layer on said sidewall of said trench;forming a precursor layer on said mask layer; converting said precursorlayer to a conglomerate layer comprised of particulates in a matrix;removing said matrix from between said particulates to expose portionsof said mask layer; and removing portions of exposed mask layer to formsaid islands.
 15. The method of claim 14, wherein said mask layer is athin silicon oxide.
 16. The method of claim 14, wherein saidparticulates are crystalline.
 17. The method of claim 14, wherein saidprecursor layer is selected from the group consisting of Si_(1−x)Ge_(x)and germosilicate glass.
 18. The method of claim 14, wherein saidconglomerate layer comprises Ge nanocrystalls in a silicon oxide matrix.19. The method of claim 14, wherein: said precursor layer comprisesSi_(1−x)Ge_(x) formed by low-pressure chemical vapor deposition; saidconglomerate layer comprises Ge nanocrystalls in a silicon oxide matrix;and said precursor layer is converted to said conglomerate layer by ahigh-pressure oxidation followed by a reduction in hydrogen.
 20. Themethod of claim 14, wherein: said precursor layer comprisesgermosilicate glass formed by atmospheric pressure chemical vapordeposition; said conglomerate layer comprises Ge nanocrystalls in asilicon oxide matrix; and said precursor layer is converted to saidconglomerate layer by annealing in hydrogen.
 21. The method of claim 14,wherein said precursor layer is between 10 and 100 Å thick.
 22. Themethod of claim 14, wherein said particulates are removed simultaneouslywith the etching of said pits.
 23. The method of claim 14, wherein saidparticulates are between 10 and 100 Å in size.
 24. The method of claim18, wherein said Ge nanocrystalls are between 10 and 100 Å in size. 25.The method of claim 13, wherein said trench conductor is selected fromthe group consisting of polysilicon, doped polysilicon, tungsten,tungsten nitride and titanium nitride.
 26. The method of claim 15,further including the step of removing said islands before forming saidnode insulator.
 27. The method of claim 13, wherein forming islands onsaid sidewalls of said trench comprises: forming a mask layer on saidsidewall of said trench; forming a precursor layer on said mask layer;converting said precursor layer to a conglomerate layer comprised ofparticulates in a matrix; removing said particulates from said matrix toexpose portions of said mask layer; and removing portions of exposedmask layer to form said islands.
 28. The method of claim 27, whereinsaid mask layer is a thin silicon oxide.
 29. The method of claim 27,wherein said particulates are crystalline.
 30. The method of claim 27,wherein said precursor layer is selected from the group consisting ofSi_(1−x)Ge_(x) and germosilicate glass.
 31. The method of claim 27,wherein said conglomerate layer comprises Ge nanocrystalls in a siliconoxide matrix.
 32. The method of claim 27, wherein: said precursor layercomprises Si_(1−x)Ge_(x) formed by low-pressure chemical vapordeposition; said conglomerate layer comprises Ge nanocrystalls in asilicon oxide matrix; and said precursor layer is converted to saidconglomerate layer by a high-pressure oxidation followed by a reductionin hydrogen.
 33. The method of claim 27, wherein: said precursor layercomprises germosilicate glass formed by atmospheric pressure chemicalvapor deposition; said conglomerate layer comprises Ge nanocrystalls ina silicon oxide matrix; and said precursor layer is converted to saidconglomerate layer by annealing in hydrogen.
 34. The method of claim 27,wherein said precursor layer is between 10 and 100 Å thick.
 35. Themethod of claim 14, wherein said particulates are between 10 and 100 Åin size.
 36. The method of claim 31, wherein said Ge nanocrystalls arebetween 10 and 100 Å in size.
 37. A trench capacitor, comprising: atrench in a silicon substrate, said trench having a sidewall; pitsetched into said sidewall; a node insulator on said pits and saidsidewall; and a trench conductor filling said trench.
 38. The trenchcapacitor of claim 37, wherein said pits are formed by: forming a masklayer on said sidewall of said trench; forming a precursor layer on saidmask layer; converting said precursor layer to a conglomerate layercomprised of particulates in a matrix; removing said matrix from betweensaid particulates to expose portions of said mask layer; removingportions of exposed mask layer to expose said sidewall; and etching saidsidewall.
 39. The trench capacitor of claim 38, wherein saidconglomerate layer comprises Ge nanocrystalls in a silicon oxide matrix.40. A dynamic random access memory cell, comprising: a FET comprising: afirst and second source/drain region formed in a silicon substrate; achannel region between said first and second source/drain regions; agate dielectric formed over said channel region; a wordline formed oversaid gate dielectric; and a bitline electrically connected to said firstsource/drain; a trench capacitor comprising: a trench in said siliconsubstrate, said trench having a sidewall; pits etched into saidsidewall; a node insulator on said pits and said sidewall; and a trenchconductor filling said trench.; and said second source/drainelectrically connected to said trench conductor.
 41. The dynamic randomaccess memory cell of claim 40, wherein said pits are formed by: forminga mask layer on said sidewall of said trench; forming a precursor layeron said mask layer; converting said precursor layer to a conglomeratelayer comprised of particulates in a matrix; removing said matrix frombetween said particulates to expose portions of said mask layer;removing portions of exposed mask layer to expose said sidewall; andetching said sidewall.
 42. The dynamic random access memory cell ofclaim 41, wherein said conglomerate layer comprises Ge nanocrystalls ina silicon oxide matrix.
 43. The dynamic random access memory cell ofclaim 40, wherein said pits are formed by: forming a mask layer on saidsidewall of said trench; forming a precursor layer on said mask layer;converting said precursor layer to a conglomerate layer comprised ofparticulates in a matrix; removing said particulates from said matrix toexpose portions of said mask layer; removing portions of exposed masklayer to expose said sidewall; and etching said sidewall.
 44. Thedynamic random access memory cell of claim 43, wherein said conglomeratelayer comprises Ge nanocrystalls in a silicon oxide matrix.